Alice walked down the corridor of tricolor light for about ten minutes, and the light ahead grew increasingly bright. It was no longer a shifting stream of code, nor transparent signal pathways—instead, it was a vast theater. The stage occupied the entire front wall, with three spotlights—red, blue, and green—shining from different angles onto the stage, each illuminating a distinct area.
At the center of the stage stood a man in a tailcoat, holding a metallic baton. He gave Alice a slight bow.
“You’ve already seen the body of the SDR in the corridor—from antenna to antenna, the signal travels the full path,” said the conductor. “Now, it’s time to meet who makes that path run.”
He waved his baton, and the stage curtain slowly parted. Behind it appeared a massive backdrop—the very same complete signal flow diagram Alice had seen in the corridor:
Antenna → RF Front-End → ADC → DDC → Baseband Processing → DUC → DAC → RF Front-End → Antenna
“This path has three segments requiring ‘workers’. Each person stands at one position and performs one type of work. Together they form a triad—none can be missing.”
He waved his baton toward the left side of the stage. A sudden burst of red light illuminated the DDC and DUC sections of the signal flow diagram.
“Let us welcome the eldest brother—FPGA!”
I. Eldest Brother FPGA—Parallel Multihand
Under the red spotlight on the left side of the stage, a broad-shouldered figure rose. He wore a red work uniform covered densely with patterns labeled “Logic Units”—thousands of identical squares arranged neatly, each resembling an independent small hand. His hands were embedded with programmable switches and interconnects, making him appear like a giant human-sized circuit board—every joint reconfigurable on demand.
His voice sounded like the simultaneous “click” of ten thousand switches closing:
“I am FPGA—Field-Programmable Gate Array. My position is DDC and DUC. High-speed digital frequency conversion, filtering, decimation, and interpolation—all require processing massive data streams simultaneously, performing billions of operations per second. There’s no waiting, no queuing, no ‘one at a time’.”
He spread his arms wide. Instantly, thousands of virtual “hands” floated above the stage—each performing a different task simultaneously: one filtering, one mixing, one decimating, one interpolating—all running concurrently, without waiting for one another.
“Without me, neither DSP nor CPU could handle these tasks—DSP calculates precisely but lacks so many hands; CPU manages broadly but must process each task sequentially.”
“So digital frequency conversion is naturally my domain. All high-speed data streams—from the ADC onward—arrive first at my palm. I translate them from high-frequency to baseband, then hand them off to my younger brother.”
He nodded toward the center of the stage, stepped back half a pace, and allowed the spotlight to shift to the other side.
II. Second Brother DSP—Arithmetic Master
The spotlight shifted from red to blue. A tall, bespectacled figure rose from the center of the stage, surrounded by rotating numeric matrices. He wore a deep-blue overcoat, each button shaped like a multiply-accumulate (MAC) unit. His fingers were long and slender, each joint marked with precise calibrations—like a slide rule.
His voice was calm and precise:
“I am DSP—Digital Signal Processor. After the eldest brother passes the baseband signal to me, I stand at the baseband processing position—modulation/demodulation, encoding/decoding, fine-tuning filter parameters, equalization algorithms. These tasks don’t require processing as many parallel data streams—but each stream demands precision and speed.”
He drew a circle in the air, instantly filling it with floating numeric matrices—thousands of numbers arranging, calculating, iterating through addition, subtraction, multiplication, and division.
“The eldest brother has ten thousand hands working in parallel—but each hand performs only the simplest operation. I, however—my instruction set is optimized specifically for digital signal processing. One instruction accomplishes what would take several instructions elsewhere. Though I’m not as fast as my elder brother—I lack ten thousand hands—each of my hands handles far more complex operations.”
“In SDR, I manage the parts requiring ‘thinking’. The eldest brother ‘receives’ the signal; I ‘understand’ it. That is my role.”
He lowered his hands, and the numeric matrices dissolved. The spotlight switched again—to green—illuminating the right side of the stage.
III. Youngest Brother CPU—Orchestration Manager
Under the green spotlight on the right side of the stage, a figure sat on a high-backed chair—not facing a circuit board, but a laptop and several screens displaying real-time system status. His attire differed entirely from his two brothers’: a charcoal-gray suit, crisp white shirt, thin-framed glasses, and a fountain pen tucked neatly into his breast pocket.
He rose, adjusted his tie—his motion unhurried and exact, as if calling a library function.
“I am CPU—Central Processing Unit. The eldest brother stands at the front end, the second brother at the core—and I stand at the topmost layer.”
He extended his right hand, and a complete operational status diagram of the SDR system materialized above the stage: device configuration, frequency settings, bandwidth selection, sample rate control, user commands, GUI display, network protocol stack transmit/receive states—countless green arrows extending downward from the top layer, connecting to the FPGA and DSP domains.
“The eldest brother handles high-speed processing—who tells him ‘what are this cycle’s operating parameters’? The second brother executes complex algorithms—who instructs him ‘which algorithm should run now’? Which frequency band to switch to? How to render the UI? How to packetize and transmit data? How does the OS schedule tasks? All these ‘management’ tasks fall to me.”
“I do not stand on the main signal path—I stand above it. Without me, the eldest and second brothers can operate—but they won’t know *what* to do—no scheduling, no control, no interaction. My presence gives the entire system direction and order.”
He opened his palms, speaking plainly yet firmly: “The eldest brother is the laborer, the second brother the technician, and I am the foreman. Three distinct roles—but remove any one, and the system cannot run.”
IV. Joint Performance
The conductor raised his baton again and tapped the stage floor three times.
“All three are present. Let them run together—”
He brought the baton down.
The red, blue, and green spotlights flared simultaneously—and the three brothers began moving in unison:
- FPGA, standing at the DDC position on the signal flow diagram, surged with crimson light—billions of data samples mixed, filtered, and decimated simultaneously. His “ten thousand hands” moved in perfect coordination, like a precision parallel loom.
- DSP, stationed at the baseband processing position on the diagram, glowed under blue light—modulation/demodulation, encoding/decoding, filter parameter optimization, and equalization algorithms flowed smoothly beneath his fingertips.
- CPU, suspended above the entire signal flow diagram, sent green control lines simultaneously to both FPGA and DSP regions—delivering frequency commands, parameter configurations, and task scheduling directives.
The signal flowed left-to-right—RF Front-End → ADC → FPGA (Red) → DSP (Blue) → Output. CPU remained continuously overhead, its green control lines never breaking.
The three beams of light—red, blue, and green—converged at the center of the stage, neither overlapping nor interfering. They resembled three parallel rivers, each responsible for one segment of the journey, ultimately flowing into the same estuary.
“This is the SDR’s heterogeneous computing architecture,” said the conductor. “The eldest brother FPGA occupies the DDC/DUC position—handling heavy lifting. The second brother DSP occupies the baseband processing position—handling precision work. The youngest brother CPU occupies the topmost layer—handling management. Each stands at a different location within the SDR’s ‘body’, fulfilling their distinct duties—only then does a single board truly ‘come alive’.”
V. A Variation of the Era—When the Second Brother Is Absent
Alice was about to applaud when she recalled a question: “In the signal flow diagram I saw in the corridor, all three brothers stood in their designated positions. But I recall seeing teardown diagrams of some SDR devices at the exhibition—none featured a standalone DSP chip?”
The conductor glanced at her and smiled. “You observed carefully. You’re absolutely right—not all SDR devices include a dedicated DSP chip.”
He lit a small lamp at the edge of the stage, casting light onto a simplified schematic of a board.
“This is the classic early-SDR architecture—three discrete chips: FPGA, DSP, and CPU, each performing its own role. But technology has advanced—FPGAs have grown increasingly powerful, capable not only of parallel processing but also integrating dedicated MAC hard cores internally; CPUs have likewise become faster, enabling software algorithms to perform digital signal processing tasks previously requiring dedicated DSP hardware.”
“So the second brother DSP…” Alice ventured hesitantly, “is he unemployed?”
The conductor shook his head: “Not unemployed—reassigned to a new workstation.”
He gestured at the schematic: “In some devices, the second brother’s ‘precision work’ has been absorbed by the eldest brother FPGA. Modern high-end FPGAs integrate DSP Slices—dedicated MAC hard cores whose computational capability rivals that of standalone DSP chips.”
“In other devices, the second brother’s tasks are replaced by software algorithms running on the youngest brother CPU. As CPUs grow faster—and especially when equipped with signal-processing-optimized instruction sets—they can execute filters and modulation/demodulation algorithms quickly enough for many applications.”
“And in some devices, FPGA and CPU are integrated onto a single chip—the eldest and youngest brothers now share the same room.”
Alice studied the repeatedly modified schematic: “Then does the ‘three brothers’ metaphor still hold?”
The conductor paused thoughtfully: “Yes, it holds. The logic of functional division remains unchanged—high-speed parallel processing belongs to FPGA; precise mathematical computation falls under DSP’s ‘responsibility’; control and management belong to CPU. Only now, those responsibilities may be fulfilled by different physical implementations. Sometimes DSP is a standalone chip; sometimes it’s merely a functional module inside an FPGA; sometimes it’s just an optimized software routine running on the CPU.”
“The responsibilities remain constant—but their physical carriers may vary. That is the reality of engineering—theoretical division of labor is clear, but practical implementation is flexible and adaptable.”
VI. Curtain Call
The three spotlights dimmed gradually. The three brothers exited the stage—the eldest brother folded away his “ten thousand hands”, the second brother closed his slide rule, and the youngest brother shut his laptop. Their figures vanished into the wings.
Yet the stage did not fall silent. The signal flow diagram on the curtain remained illuminated—the red, blue, and green markers continued blinking steadily in their respective positions, like eternal streetlights.
“This performance never ends,” the conductor peeked out from stage left, “it simply dims the spotlight. Once powered on, the SDR board keeps all three brothers working—day and night.”
Alice descended from the stage. She now understood the functional division within the SDR’s digital domain: heavy lifting belongs to FPGA, precision work to DSP, and management to CPU. Each brother occupies his designated station, collectively guiding the signal from antenna to antenna.
As she reached the theater exit, she glanced back at the signal flow diagram on the curtain—the red marker at the DDC and DUC positions still shone brightly.
The next stop: the eldest brother FPGA’s domain.
(To be continued. Next chapter: The Digital Frequency Conversion Factory—Alice will enter the eldest brother FPGA’s domain and witness the complete DDC and DUC processes: mixing, filtering, decimation, and interpolation. She will discover that reception and transmission are reverse arrangements of the same operations—and that DDC and DUC form a perfect mirror pair.)
[Chapter Four Key Concepts Recap]
| SDR Concept | Fairy-Tale Embodiment |
| FPGA’s Role in SDR | DDC/DUC—High-speed digital frequency conversion, filtering, decimation, interpolation |
| DSP’s Role in SDR | Baseband Processing—Modulation/demodulation, encoding/decoding, equalization, fine-grained filtering |
| CPU’s Role in SDR | Topmost System Layer—Control & management, protocol stack, user interface, task scheduling |
| Heterogeneous Computing Architecture | Three brothers occupy distinct positions—heavy lifting / precision work / management—collaborating in division of labor |
| Collaborative Relationship Among the Three | Signal processing chain: FPGA → DSP → CPU; CPU provides reverse control over the first two |
| Responsibility vs. Physical Carrier | A standalone DSP chip is not present in all SDR devices—the second brother’s responsibilities may be fulfilled by FPGA hard cores or CPU software; responsibilities remain fixed while carriers may vary |
Preview of Next Chapter
The Digital Frequency Conversion Factory—Alice will enter the eldest brother FPGA’s domain and witness the complete DDC and DUC processes: mixing, filtering, decimation, and interpolation. She will discover that reception and transmission are reverse arrangements of the same operations—and that DDC and DUC form a perfect mirror pair.
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